Paper Key : IRJ************836
Author: S.philemon
Date Published: 03 Nov 2022
The most promising technology for future multi-core computers is Wireless Networks-on-Chip (WNoC) because they are capable of overcoming the limitations of conventional Networks-on-Chip (NoCs). Numerous benefits of NoCs with WI have been demonstrated through in-depth analyses. Hardware and routers that are connected to WI generally consume relatively large amounts of static power. Situations where most devices are idle for long periods of time, it is a smart idea to turn off individual routers to reduce total power consumption. WNOCs with broadcast-capable antennas are also limited to only one active wireless connection, and many WIs are inactive for long periods. Therefore, we offer a fine-grained router architecture (FGRA) that consumes less power. A power-gated transceiver, which is activated by the receiving antenna whenever a signal is received, further reduces wake-up latency. NBBCs sidestep power-gated routers, alleviating routing delay and congestion further. The buffers also consume a high amount of power dynamically and their power consumption increases rapidly with increasing packet flow rates. Dynamically and statically, the Easy Pass Router reduces power consumption significantly. This proposed architecture improves NoCs in terms of both energy efficiency and performance. In periods of low traffic, switching mechanisms could be used instead of complex pipelined routers to save energy
DOI LINK : 10.56726/IRJMETS30946
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